The present disclosure relates generally to semiconductor devices, and more particularly to nonvolatile memory devices. Still more particularly, the present disclosure relates to reference voltage generator circuits and methods for controlling a reference voltage in nonvolatile memory devices.
Nonvolatile memory devices such as flash memory and electrically-erasable-programmable-read-only memory (EEPROM) utilize a plurality of internal memory arrays that can be programmed to last indefinitely. Additional control circuitry is embedded in these devices for a number of purposes, including reference voltage generation for sense amplifiers. However, it is understood by those skilled in the art that the embedded circuitries and the methods by which the said circuitries are embedded may vary from time to time, depending on the desired functionality of the memory device.
Typically, memory cells in a memory array are arranged along rows and columns. The gates of the cells along each row are connected together, thereby forming a word line. The drains of the cells along each column are connected together, thereby forming a bit line. The selection of a word line and a bit line determines which memory cell is selected.
Memory cells are typically programmed by tunneling electrons into a memory cell. The presence of a charge bias determines the value (“1” or “0”) of the memory cell. Stored electrons can then be read electrically by detecting the resistance of the said memory cell, since the resistance of the said memory cell is dependent upon the magnitude of charge bias. By selecting the appropriate word line and bit line through a row address decoder and a column address decoder, respectively, the charge bias of the appropriate memory cell may be determined.
Because of variations in semiconductor memory designs and variations in the magnitude of tunneling under various programming setups, resistance often varies across different designs and setups. Therefore, a unique reference for a particular semiconductor memory design and setup is usually required such that it can be compared against the actual resistance in memory cells. The bit line signal for each memory cell is regenerated by a sense amplifier, which defines a “1” or a “0” of the said memory cell by determining whether the resistance of the said memory cell is above or below a reference resistance. This threshold resistance is stored in a “half-cell” whose resistance is usually midway between when a material is fully-resisted or lowly-resisted.
Since a reference voltage generator circuitry is responsible for all sense amplifiers across all bit lines in a memory block, as the width of bit line input/output (I/O) increases, capacitance loading across all bit lines will correspondingly increase. As such, the reference voltage generator circuitry, which generates the threshold voltage for all sense amplifiers, will experience a correspondingly large capacitance loading. During a reading cycle, the reference voltage generated by a bias reference voltage generator circuit needs to discharge. As capacitance loading increases, the time required to discharge before the reference voltage is said to be “ready” increases correspondingly. If the reference voltage is not “ready” before memory read operations begin, an erroneous reference voltage may be fed into the sense amplifier, which in turn may return an erroneous memory reading.
As flash memory and EEPROM applications call for wider I/O requirements, bit line capacitance load will correspondingly increase. This dramatic increase in capacitance load in turn requires any circuitry that generates a reference voltage to either increase its discharge speed, or be independent thereof.
Desirable in the art of semiconductor memory design are additional methods with which a better control of sense amplifier reference voltage in nonvolatile memories can be achieved.